www.nortonkit.com 18 अक्तूबर 2013
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Combinational Logic: [Basic Gates] [Derived Gates] [The XOR Function] [Binary Addition] [Negative Numbers and Binary Subtraction] [Multiplexer] [Decoder/Demultiplexer] [Boolean Algebra]
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Alternate Flip-Flop Circuits: [D Flip-Flop Using NOR Latches] [CMOS Flip-Flop Construction]
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Registers: [Shift Register (S to P)] [Shift Register (P to S)]
The 555 Timer: [555 Internals and Basic Operation] [555 Application: Pulse Sequencer]
555 Application: Pulse Sequencer

One requirement in certain digital circuits is for the generation of a series of pulses in time sequence, but on different lines. The pulse widths may or may not be the same, but they must occur one after the other, and therefore cannot come from the same source.

Sometimes pulses are required to overlap, or there must be a set delay following the end of one pulse before another pulse begins. Or, One pulse must begin a set time after another begins. The possible variations in timing requirements are almost endless, and many different approaches have been used to provide pulses with the necessary timing relationships. One inexpensive method that is perfectly satisfactory in many applications is to use interconnected 555 timers to generate the necessary timing intervals.

In the circuit shown above, we see three 555 timers, all configured in monostable mode. Each one, from left to right, triggers the next at the end of its timing interval. The resulting pulse timing is shown in the timing diagram to the right.

The sequence starts with the falling edge of the incoming trigger pulse. That edge triggers timer A, causing output A to go high. At this point, the incoming trigger pulse can either stay low or go high; it is no longer important.

Output A will remain high for the duration of its timing interval, and then fall back to its low state. At this time, it triggers timer B. Output B therefore goes high as output A falls. The same thing happens again at the end of the B timing interval; output B falls and triggers timer C.

At the end of the C timing interval, the sequence is over and all timers are quiescent, awaiting the arrival of the next triggering signal.

This time, the circuit is wired so that the incoming trigger signal is applied to both timers A and B. However, B's timing interval is very short, so it triggers timer C while the A output is still high. Depending on the designed timing intervals, C can easily be triggered and finish its timing interval while A is still active. Or, C can remain active after A falls back to its quiescent state.

Any number of 555 timers can be sequentially or jointly triggered with this kind of arrangement, and each timer still has its own individually-controlled timing interval. The possible combinations are endless, and independent pulses can overlap or not according to the needs of the application.

The initial triggering signal can come from any source. It can even be from another 555 timer, operating in astable mode. In that case, this kind of circuit is self-starting and will operate continuously.

It is also possible to trigger this sort of circuit manually, using a momentary-contact pushbutton to provide the triggering pulse. Or it could be some sort of sensor device, triggering the circuit upon recognition of some external condition. Thus, the circuit can be triggered by any kind of event, just as it can be used to control any kind of circuit.

There is one drawback to using daisy-chained 555 timers in this fashion. Once a 555 timer in monostable mode has been triggered, it cannot be re-triggered and the timing interval cannot be changed (at least without the addition of external circuitry to accomplish that). Therefore, if a second trigger pulse arrives while the input timer(s) are still active, it will be ignored. A worse possibility exists for the second example above: If the B interval has been completed but the A interval has not been completed when a new trigger pulse is received, timer B will be triggered but timer A will ignore it. If the timing relationship between the A and C pulses is critical, this could cause problems.

Nevertheless, this type of circuit can be highly versatile and useful, provided appropriate precautions are taken to ensure that such errors will not occur.

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