|www.nortonkit.com||18 अक्तूबर 2013|
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|Combinational Logic:||[Basic Gates] [Derived Gates] [The XOR Function] [Binary Addition] [Negative Numbers and Binary Subtraction] [Multiplexer] [Decoder/Demultiplexer] [Boolean Algebra]|
|Sequential Logic:||[RS NAND Latch] [RS NOR Latch] [Clocked RS Latch] [RS Flip-Flop] [JK Flip-Flop] [D Latch] [D Flip-Flop] [Flip-Flop Symbols] [Converting Flip-Flop Inputs]|
|Alternate Flip-Flop Circuits:||[D Flip-Flop Using NOR Latches] [CMOS Flip-Flop Construction]|
|Counters:||[Basic 4-Bit Counter] [Synchronous Binary Counter] [Synchronous Decimal Counter] [Frequency Dividers] [Counting in Reverse] [The Johnson Counter]|
|Registers:||[Shift Register (S to P)] [Shift Register (P to S)]|
|The 555 Timer:||[555 Internals and Basic Operation] [555 Application: Pulse Sequencer]|
|A Synchronous Binary Counter|
In our initial discussion on counters (A Basic Digital Counter), we noted the need to have all flip-flops in a counter to operate in unison with each other, so that all bits in the ouput count would change state at the same time. To accomplish this, we need to apply the same clock pulse to all flip-flops.
However, we do not want all flip-flops to change state with every clock pulse. Therefore, we'll need to add some controlling gates to determine when each flip-flop is allowed to change state, and when it is not. This requirement denies us the use of T flip-flops, but does require that we still use edge-triggered circuits. We can use either RS or JK flip-flops for this; we'll use JK flip-flops for the demonstrations on this page.
To determine the gates required at each flip-flop input, let's start by drawing up a truth table for all states of the counter. Such a table is shown to the right.
Looking first at output A, we note that it must change state with every input clock pulse. Therefore, we could use a T flip-flop here if we wanted to. We won't do so, just to make all of our flip-flops the same. But even with JK flip-flops, all we need to do here is to connect both the J and K inputs of this flip-flop to logic 1 in order to get the correct activity.
Flip-flop B is a bit more complicated. This output must change state only on every other input clock pulse. Looking at the truth table again, output B must be ready to change states whenever output A is a logic 1, but not when A is a logic 0. If we recall the behavior of the JK flip-flop, we can see that if we connect output A to the J and K inputs of flip-flop B, we will see output B behaving correctly.
Continuing this line of reasoning, output C may change state only when both A and B are logic 1. We can't use only output B as the control for flip-flop C; that will allow C to change state when the counter is in state 2, causing it to switch directly from a count of 2 to a count of 7, and again from a count of 10 to a count of 15 not a good way to count. Therefore we will need a two-input AND gate at the inputs to flip-flop C. Flip-flip D requires a three-input AND gate for its control, as outputs A, B, and C must all be at logic 1 before D can be allowed to change state.
The resulting circuit is shown in the demonstration below.
When we started our look into counters, we noted a lot of applications involving numeric displays: clocks, ovens, microwave ovens, VCRs, etc. These applications require a decimal count in most cases, and a count from 0 to 5 for some digits in a clock display. Can we use a method of gating, such as we used above in the synchronous binary counter, to shorten the counting sequence to the appropriate extent?
Obviously there is a way, since digital clocks and watches do exist and do work. Starting on the next page, we'll see how.
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