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Sequential Logic: [RS NAND Latch] [RS NOR Latch] [Clocked RS Latch] [RS Flip-Flop] [JK Flip-Flop] [D Latch] [D Flip-Flop] [Flip-Flop Symbols] [Converting Flip-Flop Inputs]
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Counters: [Basic 4-Bit Counter] [Synchronous Binary Counter] [Synchronous Decimal Counter] [Frequency Dividers] [Counting in Reverse] [The Johnson Counter]
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Frequency Dividers
A flip-flop performing frequency division

If we apply a fixed-frequency pulse train to a counter, rather than individual pulses coming at random intervals, we begin to notice some interesting characteristics, and some useful relationships between the input clock signal and the output signals.

Consider a single flip-flop with a continuous succession of clock pulses at a fixed frequency, such as the one shown to the right. We note three useful facts about the output signals seen at Q and Q':

The duty cycle of any rectangular waveform refers to the percentage of the full cycle that the signal remains at logic 1. If the signal spends half its time at logic 1 and the other half at logic 0, we have a waveform with a 50% duty cycle. This describes a perfect, symmetrical square wave.

Divide-by-three counter.

Frequency division by an odd number is also possible. The circuit to the left is a demonstration of a divide-by-3 counter. No gates are required to control the sequence if JK flip-flops are used; feeding the output signals back to the appropriate inputs is sufficient.

Of course, it is not possible to get a symmetrical (50% duty cycle) square wave with this circuit. The A output is at logic 1 for two clock pulses out of three; the B output is at logic 1 for one clock pulse out of three. Thus, duty cycles of 1/3 (33.333%) and 2/3 (66.667%) are available.

This rendition of a divide-by-5 counter actually follows the normal decimal (or binary) count from zero through four. The primary control feature is the feedback from the C' output to flip-flop A's J input. This feedback prevents flip-flop A from switching from logic 0 to logic 1 in an effort to go from a count of four to a count of five. At the same time, the C output is applied to flip-flop C's K input to force flip-flop C to reset on the next clock pulse.

This particular arrangement is often combined with a single flip-flop in an IC package. The combination can then be used either as a normal decimal counter or as a divide-by-10 counter with a true square-wave output.

Divide-by-5 counter.

Divide-by-5 counter with no gates.

If it is not necessary to maintain a standard binary counting sequence, we can often interconnect the flip-flops so as to eliminate the need for any extra gates, as shown to the left. Note that the K inputs to both flip-flops A and B are connected to logic 1. As a result, outputs A and B will remain at logic 1 for only one clock pulse at a time, and will then reset to logic 0. Output C will toggle after B goes to logic 1.

Output C has a 40% duty cycle. Outputs A and B produce two output pulses for each pulse from C, but not at equal intervals. The counting sequence is 0, 1, 2, 5, 6, 0, etc.

This counter circuit actually has a flaw as shown: if it powers up in state 4 (A = 0, B = 0, C = 1), it will remain in that state and be unable to change at all. To correct this, we can disconnect C's K input from output B, and connect it to output A' instead. Now the first clock pulse will force the circuit to state 0 (000), from which the count will proceed normally. This change will not affect the normal counting sequence, because a logic 1 at the K input cannot prevent the flip-flop from changing to a logic 1, and would force C back to a logic 0 at the same time it would change anyway.

Other counting sequences are also possible, of course. If a need exists to have two or more signals in a particular frequency relationship with each other, some extension or variation on the circuits shown here can be designed to supply the need.

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