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Sequential Logic: [RS NAND Latch] [RS NOR Latch] [Clocked RS Latch] [RS Flip-Flop] [JK Flip-Flop] [D Latch] [D Flip-Flop] [Flip-Flop Symbols] [Converting Flip-Flop Inputs]
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Converting Flip-Flop Input Types
Converting an RS flip-flop to T operation.

Sometimes it just happens that you need a particular type of flip-flop for a specific application, but all you have available is another type. This often happens with an application needing T flip-flops, since these are not generally available in commercial packages. Rather, it is necessary to re-wire an available type to perform as a T device.

Fortunately, this is not hard. We've already seen that a JK flip-flop with its J and K inputs connected to a logic 1 will operate as a T flip-flop. Converting an RS flip-flop involves a bit more, as shown to the right. However, the simple feedback connections shown will ensure that the S and R inputs will always tell the flip-flop to change state at each clock pulse.

Converting a D flip-flop to T operation is quite similar; the Q' output is connected back to the D input.

Converting an RS flip-flop to D operation.

Another conversion that is required on occasion is to convert an RS flip-flop to D operation. This change eliminates the possibility of an illegal input condition, which could otherwise cause spurious results in some applications.

In this case, we do need to add an inverter to supply the R input signal, as shown to the left.

Converting a D flip-flop to JK operation.

A much more complicated circuit, shown to the right, is the gating structure needed to convert a D flip-flop to JK operation. This circuit implements the logical truth that D = JQ' + K'Q.

This input circuit is actually used more frequently than you might think. CMOS flip-flops are typically constructed as D types because of the nature of their internal operation. Commercial CMOS JK flip-flops, such as the 4013, then add this circuit to the input in order to get JK operation.

This approach eliminates the internal latching effect, or "ones catching," that occurs with the general JK master-slave flip-flop. The J and K input signals must be present at the time the clock signal falls to logic 0, in order to affect the new output state.

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